Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation
This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gat...
Saved in:
Main Authors: | , , , |
---|---|
Format: | Article |
Language: | English |
Published: |
Springer
2017
|
Online Access: | http://psasir.upm.edu.my/id/eprint/61306/1/Designing%20and%20implementing%20a%20novel%20single%20IFFT%20scrambling%20PAPR%20reduction%20scheme%20in%20OFDM%20systems%20using%20FPGA%20with%20hardware%20co-simulation.pdf http://psasir.upm.edu.my/id/eprint/61306/ https://link.springer.com/article/10.1007/s11277-017-4123-5 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Universiti Putra Malaysia |
Language: | English |
Internet
http://psasir.upm.edu.my/id/eprint/61306/1/Designing%20and%20implementing%20a%20novel%20single%20IFFT%20scrambling%20PAPR%20reduction%20scheme%20in%20OFDM%20systems%20using%20FPGA%20with%20hardware%20co-simulation.pdfhttp://psasir.upm.edu.my/id/eprint/61306/
https://link.springer.com/article/10.1007/s11277-017-4123-5