Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation

This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gat...

Full description

Saved in:
Bibliographic Details
Main Authors: Al-Hussaini, Khalid, Mohd Ali, Borhanuddin, Varahram, Pooria, Hashim, Shaiful Jahari
Format: Article
Language:English
Published: Springer 2017
Online Access:http://psasir.upm.edu.my/id/eprint/61306/1/Designing%20and%20implementing%20a%20novel%20single%20IFFT%20scrambling%20PAPR%20reduction%20scheme%20in%20OFDM%20systems%20using%20FPGA%20with%20hardware%20co-simulation.pdf
http://psasir.upm.edu.my/id/eprint/61306/
https://link.springer.com/article/10.1007/s11277-017-4123-5
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Universiti Putra Malaysia
Language: English
id my.upm.eprints.61306
record_format eprints
spelling my.upm.eprints.613062018-07-25T08:18:54Z http://psasir.upm.edu.my/id/eprint/61306/ Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation Al-Hussaini, Khalid Mohd Ali, Borhanuddin Varahram, Pooria Hashim, Shaiful Jahari This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gate array. In this technique, the output of inverse fast Fourier transforms (IFFT) is partitioned into M subblocks, which are subsequently interleaved. Then, a new optimization scheme is introduced in which only a single two phase sequence need to be applied. Unlike the conventional partial transmit sequence (C-PTS) which needs M-IFFT blocks and WM−1 iterations, the proposed technique requires only a single IFFT block and M iterations. These features significantly reduce processing time and less computation that leads to reduced complexity. Simulation results demonstrate that the new technique can effectively reduce the complexity up to 99.95% compared with the conventional PTS (C-PTS) technique and yields good PAPR performance. The good PAPR performance arises from the effect of both the data interleaving and the new optimization technique. Through the comparison of performance between simulation and hardware, it is distinctly illustrated that the designed hardware block diagram is as workable as the simulation, and the difference of the result is only 0.1 dB. Springer 2017 Article PeerReviewed text en http://psasir.upm.edu.my/id/eprint/61306/1/Designing%20and%20implementing%20a%20novel%20single%20IFFT%20scrambling%20PAPR%20reduction%20scheme%20in%20OFDM%20systems%20using%20FPGA%20with%20hardware%20co-simulation.pdf Al-Hussaini, Khalid and Mohd Ali, Borhanuddin and Varahram, Pooria and Hashim, Shaiful Jahari (2017) Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation. Wireless Personal Communications, 95 (4). 4763 - 4788. ISSN 0929-6212; ESSN: 1572-834X https://link.springer.com/article/10.1007/s11277-017-4123-5 10.1007/s11277-017-4123-5
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
description This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gate array. In this technique, the output of inverse fast Fourier transforms (IFFT) is partitioned into M subblocks, which are subsequently interleaved. Then, a new optimization scheme is introduced in which only a single two phase sequence need to be applied. Unlike the conventional partial transmit sequence (C-PTS) which needs M-IFFT blocks and WM−1 iterations, the proposed technique requires only a single IFFT block and M iterations. These features significantly reduce processing time and less computation that leads to reduced complexity. Simulation results demonstrate that the new technique can effectively reduce the complexity up to 99.95% compared with the conventional PTS (C-PTS) technique and yields good PAPR performance. The good PAPR performance arises from the effect of both the data interleaving and the new optimization technique. Through the comparison of performance between simulation and hardware, it is distinctly illustrated that the designed hardware block diagram is as workable as the simulation, and the difference of the result is only 0.1 dB.
format Article
author Al-Hussaini, Khalid
Mohd Ali, Borhanuddin
Varahram, Pooria
Hashim, Shaiful Jahari
spellingShingle Al-Hussaini, Khalid
Mohd Ali, Borhanuddin
Varahram, Pooria
Hashim, Shaiful Jahari
Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation
author_facet Al-Hussaini, Khalid
Mohd Ali, Borhanuddin
Varahram, Pooria
Hashim, Shaiful Jahari
author_sort Al-Hussaini, Khalid
title Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation
title_short Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation
title_full Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation
title_fullStr Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation
title_full_unstemmed Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation
title_sort designing and implementing a novel single ifft scrambling papr reduction scheme in ofdm systems using fpga with hardware co-simulation
publisher Springer
publishDate 2017
url http://psasir.upm.edu.my/id/eprint/61306/1/Designing%20and%20implementing%20a%20novel%20single%20IFFT%20scrambling%20PAPR%20reduction%20scheme%20in%20OFDM%20systems%20using%20FPGA%20with%20hardware%20co-simulation.pdf
http://psasir.upm.edu.my/id/eprint/61306/
https://link.springer.com/article/10.1007/s11277-017-4123-5
_version_ 1643837542904102912