Designing and implementing a novel single IFFT scrambling PAPR reduction scheme in OFDM systems using FPGA with hardware co-simulation
This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gat...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Springer
2017
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| Online Access: | http://psasir.upm.edu.my/id/eprint/61306/1/Designing%20and%20implementing%20a%20novel%20single%20IFFT%20scrambling%20PAPR%20reduction%20scheme%20in%20OFDM%20systems%20using%20FPGA%20with%20hardware%20co-simulation.pdf http://psasir.upm.edu.my/id/eprint/61306/ https://link.springer.com/article/10.1007/s11277-017-4123-5 |
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| Institution: | Universiti Putra Malaysia |
| Language: | English |
| Summary: | This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gate array. In this technique, the output of inverse fast Fourier transforms (IFFT) is partitioned into M subblocks, which are subsequently interleaved. Then, a new optimization scheme is introduced in which only a single two phase sequence need to be applied. Unlike the conventional partial transmit sequence (C-PTS) which needs M-IFFT blocks and WM−1 iterations, the proposed technique requires only a single IFFT block and M iterations. These features significantly reduce processing time and less computation that leads to reduced complexity. Simulation results demonstrate that the new technique can effectively reduce the complexity up to 99.95% compared with the conventional PTS (C-PTS) technique and yields good PAPR performance. The good PAPR performance arises from the effect of both the data interleaving and the new optimization technique. Through the comparison of performance between simulation and hardware, it is distinctly illustrated that the designed hardware block diagram is as workable as the simulation, and the difference of the result is only 0.1 dB. |
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