Scheduling Power-Constrained Tests through the SoC Functional Bus

This paper proposes a test methodology for core-based testing of System-on-Chips by utilizing the functional bus as a test access mechanism. The functional bus is used as a transportation channel for the test stimuli and responses from a tester to the cores under test (CUT). To enable test concurren...

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Bibliographic Details
Main Authors: Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Orailoglu, Alex, Fujiwara, Hideo
Format: Article
Published: Institute of Electronics, Information and Communication Engineers, Japan (IEICE) 2008
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Online Access:http://eprints.utp.edu.my/3594/1/fawnizu_ieice1-revised3.pdf
http://www.ieice.org/eng/books/trans.html
http://eprints.utp.edu.my/3594/
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Institution: Universiti Teknologi Petronas
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