Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit

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Bibliographic Details
Main Authors:	Maher Assaad, Fawnizu Azmadi bin Hussin
Format:	Citation Index Journal
Published:	2012
Online Access:	http://eprints.utp.edu.my/9795/
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Institution:	Universiti Teknologi Petronas

id	my.utp.eprints.9795
record_format	eprints
spelling	my.utp.eprints.97952013-04-07T05:33:05Z Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit Maher Assaad, Fawnizu Azmadi bin Hussin, 2012 Citation Index Journal NonPeerReviewed Maher Assaad, and Fawnizu Azmadi bin Hussin, (2012) Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit. [Citation Index Journal] http://eprints.utp.edu.my/9795/
institution	Universiti Teknologi Petronas
building	UTP Resource Centre
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Teknologi Petronas
content_source	UTP Institutional Repository
url_provider	http://eprints.utp.edu.my/
format	Citation Index Journal
author	Maher Assaad, Fawnizu Azmadi bin Hussin,
spellingShingle	Maher Assaad, Fawnizu Azmadi bin Hussin, Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit
author_facet	Maher Assaad, Fawnizu Azmadi bin Hussin,
author_sort	Maher Assaad,
title	Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit
title_short	Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit
title_full	Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit
title_fullStr	Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit
title_full_unstemmed	Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit
title_sort	design and fpga implementation of pll-based quarter-rate clock and data recovery circuit
publishDate	2012
url	http://eprints.utp.edu.my/9795/
_version_	1738655791179628544

Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit

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