Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit

Saved in:
Bibliographic Details
Main Authors: Maher Assaad, Fawnizu Azmadi bin Hussin
Format: Citation Index Journal
Published: 2012
Online Access:http://eprints.utp.edu.my/9795/
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Universiti Teknologi Petronas
Be the first to leave a comment!
You must be logged in first