Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing

Semiconductor including integrated circuit (IC) is an expensive and complicated process. The trend of semiconductor packaging is going towards better performance with lower power consumption packages. Thus, the single-die packaging trend has evolved into multi-die packaging. The evolution of multi-...

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Main Authors:	Mohd Fazil, Azlan Faizal, Mohd Shaharanee, Izwan Nizal, Mohd Jamil, Jastini, Ang, Jin Sheng
Format:	Article
Language:	English
Published:	kansai university, japan 2020
Subjects:	QA75 Electronic computers. Computer science
Online Access:	http://repo.uum.edu.my/28159/1/TRKU%2062%2017%202020%203625%203630.pdf http://repo.uum.edu.my/28159/ https://www.kansaiuniversityreports.com/search-article
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Institution:	Universiti Utara Malaysia
Language:	English

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spelling	my.uum.repo.281592021-02-07T05:31:32Z http://repo.uum.edu.my/28159/ Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing Mohd Fazil, Azlan Faizal Mohd Shaharanee, Izwan Nizal Mohd Jamil, Jastini Ang, Jin Sheng QA75 Electronic computers. Computer science Semiconductor including integrated circuit (IC) is an expensive and complicated process. The trend of semiconductor packaging is going towards better performance with lower power consumption packages. Thus, the single-die packaging trend has evolved into multi-die packaging. The evolution of multi-die packaging requires more tools and processing steps in the assembly process. Furthermore, any die is tested at Class, and detected faulty will cause the whole package to be scrapped. These factors cause a bigger loss in production yield to compare to the single-die packaging. A new framework is suggested for model training and evaluation for the application of machine learning in the semiconductor test. The proposed new framework will be able to provide a range of possible recall rates from minimum to maximum to identify which machine learning algorithms specifically. kansai university, japan 2020 Article PeerReviewed application/pdf en http://repo.uum.edu.my/28159/1/TRKU%2062%2017%202020%203625%203630.pdf Mohd Fazil, Azlan Faizal and Mohd Shaharanee, Izwan Nizal and Mohd Jamil, Jastini and Ang, Jin Sheng (2020) Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing. Technology Reports of Kansai University, 62 (7). pp. 3625-3630. ISSN 04532198 https://www.kansaiuniversityreports.com/search-article
institution	Universiti Utara Malaysia
building	UUM Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Utara Malaysia
content_source	UUM Institutional Repository
url_provider	http://repo.uum.edu.my/
language	English
topic	QA75 Electronic computers. Computer science
spellingShingle	QA75 Electronic computers. Computer science Mohd Fazil, Azlan Faizal Mohd Shaharanee, Izwan Nizal Mohd Jamil, Jastini Ang, Jin Sheng Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing
description	Semiconductor including integrated circuit (IC) is an expensive and complicated process. The trend of semiconductor packaging is going towards better performance with lower power consumption packages. Thus, the single-die packaging trend has evolved into multi-die packaging. The evolution of multi-die packaging requires more tools and processing steps in the assembly process. Furthermore, any die is tested at Class, and detected faulty will cause the whole package to be scrapped. These factors cause a bigger loss in production yield to compare to the single-die packaging. A new framework is suggested for model training and evaluation for the application of machine learning in the semiconductor test. The proposed new framework will be able to provide a range of possible recall rates from minimum to maximum to identify which machine learning algorithms specifically.
format	Article
author	Mohd Fazil, Azlan Faizal Mohd Shaharanee, Izwan Nizal Mohd Jamil, Jastini Ang, Jin Sheng
author_facet	Mohd Fazil, Azlan Faizal Mohd Shaharanee, Izwan Nizal Mohd Jamil, Jastini Ang, Jin Sheng
author_sort	Mohd Fazil, Azlan Faizal
title	Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing
title_short	Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing
title_full	Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing
title_fullStr	Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing
title_full_unstemmed	Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing
title_sort	framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing
publisher	kansai university, japan
publishDate	2020
url	http://repo.uum.edu.my/28159/1/TRKU%2062%2017%202020%203625%203630.pdf http://repo.uum.edu.my/28159/ https://www.kansaiuniversityreports.com/search-article
_version_	1691735345076371456

Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing

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