Experimental modules on integrated circuit design using tanner for 0.18um CMOS process

• Main Authors: Amis, Paul Anthony M., Endaya, Renard Ryan, Sy, Terence Mervin M.
• Format: text
• Language: English
• Published: Animo Repository 2014
• Subjects: Integrated circuits > Design and construction; Engineering
• Online Access: https://animorepository.dlsu.edu.ph/etd_bachelors/11461
• Institution: De La Salle University

The development in integrated circuit fabrication demands smaller transistors in order to fit more inside thus leading to faster circuits. Previous technology such as 0.5um, and 0.25um are going to be replaced by 0.18um technology in order to keep up with technology. This paper aims to create an environment for 0.18um in Tanner EDA tools and produce experiment manuals for students to learn the basics of integrated circuit fabrication. We have used the Taiwan Semiconductor (TSMC) 0.18um design rules and imported them into Tanner EDA tools. Experiment manuals tackles on topics such as layout using L-Edit, simulation with T-Spice, creation of digital and analog circuits, Layout vs. Schematic, and creation of bonding pads. We have verified that the environment is indeed correct by importing a 0.18um op-amp circuit from Synopsys into our created 0.18um environment. All the layers were imported and the circuit has passed our DRC with no errors. Moreover, we have successfully created experiment manuals for 2-stage op amp, master slave d flip flop, 2 bit counter, NAND, parameter extraction, NOR, pass transistor, bonding pads, resistors, capacitors, and inverters in 0.18um technology. The experiments are designed to teach the students the design flow for integrated circuits fabrication.