FPGA-based built-in self test for a 4-bit BCD adder

• Main Authors: Bergonio, Norwynn B., Halili, Rafael F., Lim, Maris Mei P., Santiago, Chelyne G.
• Format: text
• Language: English
• Published: Animo Repository 2010
• Subjects: Field programmable gate arrays; Digital integrated circuits; Electronic digital computers; Electronic circuits > Testing
• Online Access: https://animorepository.dlsu.edu.ph/etd_bachelors/14693
• Institution: De La Salle University

In this paper, an FPGA-based built in self-test program for a 4-bit BCD adder is presented. The program can detect stuck at faults and bridging faults. The main components of the program include: circuit under test, main controller, test pattern generator, scan chain and the output response analyzer. For the stuck at fault, the main controller controls the test pattern generator which in turn sends out test patterns to the 4-bit BCD adder. In order to test the 4-bit BCD adder, the scan chain is inserted at each stage. The scan chain allows the test patterns to test each node of the BCD adder. The corresponding test output of the system is displayed in the LED’s found within the FPGA board. For the bridging fault, it cannot be implemented within the FPGA because it is a design rule violation of the FPGA itself, hence an external 2-bit adder circuit is instead constructed. The external circuit is connected to the FPGA, which contains the test pattern for this type of fault. Basically, the VHDL code used to test the stuck-at-faults is also used to test the bridging fault. The stuck-at-fault system detects the errors per node and it can detect varying faults from all nodes simultaneously. All stuck-at-one and stuck-at-zero faults were detected. The bridging fault can detect errors at the input level but detect only one error at a time.