Design criteria assessment for ball grid array semiconductor packaging based on thermomechanical simulation and crack analysis

• Main Author: Lim, Niño Rigo Emil G.
• Format: text
• Language: English
• Published: Animo Repository 2018
• Subjects: Semiconductors; Semiconductor storage devices
• Online Access: https://animorepository.dlsu.edu.ph/etd_masteral/5441
• Institution: De La Salle University

With notable advancements in the semiconductor devices, moving forward towards smaller and denser designs congruous with Moores Law, the semiconductor packages have to keep up with the significant changes in order to prevent the semiconductor chips from damages caused by both internal and external factors. A finite element model was validated using the material properties and dimensions from a previous study that compared 2D FEM results to actual experimental data. The results have shown to be not significantly different from the 2D model and experimental results. The developed model was then used to assess various material properties and dimension, to identify the factors with main significant effect on the crack propagation in a silicon die. The factors identified are die thickness, substrate in-plane CTE(x&y-axes), mold glass transition temperature, and initial crack length. A central composite design of experiment was implemented to develop a prediction model and expression that is able to predict the value of energy release rate in the die chip. The prediction profiler can be used to identify the critical parametric values of the identified factors that contribute to the crack propagation. The prediction model was then used to determine the energy release rates for the runs generated in the central composite design. Statistical test has shown that the values from the simulation runs and predicted by the model are not significantly different.