A synthesizable verilog model of an adaptive differential pulse code modulation (ADPCM) codec

A synthesizable verilog model of an adaptive differential pulse code modulation (ADPCM) codec

This thesis proposes to make a Synthesizable Verilog Hardware Description Language (HDL) model of an Adaptive Differential Pulse Code Modulation (ADPCM) codec. The ADPCM model is intended to be used for toll-quality speech compression and would be coded in Verilog HDL's Register Transfer Level...

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Bibliographic Details
Main Author: Yao, Stephen U.
Format: text
Language:English
Published: Animo Repository 1997
Subjects:
Pulse code modulation
Digital electronics
Verilog (Computer hardware description language)
Integrated circuits > Computer simulation
Engineering
Online Access:https://animorepository.dlsu.edu.ph/etd_masteral/1839
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Institution: De La Salle University
Language: English
Description
Summary:This thesis proposes to make a Synthesizable Verilog Hardware Description Language (HDL) model of an Adaptive Differential Pulse Code Modulation (ADPCM) codec. The ADPCM model is intended to be used for toll-quality speech compression and would be coded in Verilog HDL's Register Transfer Level (RTL) for synthesizability. Synthesizability assures the designer of the implementability of the design.

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