Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter
This study focuses on the design of signed 10-bit Delta-Sigma Analog to- Digital Converter (DS-ADC) that can operate at 1.5V supply using 0.35um technology that is normally intended to work at 3.3V. The design has an oversampling ratio (OSR) of 128, a signal bandwidth of 4 KHz, which covers the huma...
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| Main Authors: | , |
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| Format: | text |
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Animo Repository
2011
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| Subjects: | |
| Online Access: | https://animorepository.dlsu.edu.ph/faculty_research/12094 |
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| Institution: | De La Salle University |
| Summary: | This study focuses on the design of signed 10-bit Delta-Sigma Analog to- Digital Converter (DS-ADC) that can operate at 1.5V supply using 0.35um technology that is normally intended to work at 3.3V. The design has an oversampling ratio (OSR) of 128, a signal bandwidth of 4 KHz, which covers the human voice bandwidth, and a maximum sampling frequency of 1.024 MHz. The design is composed of a 1st Order Delta-Sigma Modulator and a 2nd Order Cascaded Integrator Comb (CIC) decimation filter as its digital signal processor (DSP). The DS-ADC is characterized and implemented using Tanner tools and LTSpice tool. |
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