Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter
This study focuses on the design of signed 10-bit Delta-Sigma Analog to- Digital Converter (DS-ADC) that can operate at 1.5V supply using 0.35um technology that is normally intended to work at 3.3V. The design has an oversampling ratio (OSR) of 128, a signal bandwidth of 4 KHz, which covers the huma...
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2011
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oai:animorepository.dlsu.edu.ph:faculty_research-136202024-02-12T08:09:32Z Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter Abad, Alexander C. Yap, Roderick Y. This study focuses on the design of signed 10-bit Delta-Sigma Analog to- Digital Converter (DS-ADC) that can operate at 1.5V supply using 0.35um technology that is normally intended to work at 3.3V. The design has an oversampling ratio (OSR) of 128, a signal bandwidth of 4 KHz, which covers the human voice bandwidth, and a maximum sampling frequency of 1.024 MHz. The design is composed of a 1st Order Delta-Sigma Modulator and a 2nd Order Cascaded Integrator Comb (CIC) decimation filter as its digital signal processor (DSP). The DS-ADC is characterized and implemented using Tanner tools and LTSpice tool. 2011-01-01T08:00:00Z text https://animorepository.dlsu.edu.ph/faculty_research/12094 Faculty Research Work Animo Repository Analog-to-digital converters Electrical and Electronics |
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De La Salle University |
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Philippines Philippines |
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DLSU Institutional Repository |
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Analog-to-digital converters Electrical and Electronics |
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Analog-to-digital converters Electrical and Electronics Abad, Alexander C. Yap, Roderick Y. Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter |
| description |
This study focuses on the design of signed 10-bit Delta-Sigma Analog to- Digital Converter (DS-ADC) that can operate at 1.5V supply using 0.35um technology that is normally intended to work at 3.3V. The design has an oversampling ratio (OSR) of 128, a signal bandwidth of 4 KHz, which covers the human voice bandwidth, and a maximum sampling frequency of 1.024 MHz. The design is composed of a 1st Order Delta-Sigma Modulator and a 2nd Order Cascaded Integrator Comb (CIC) decimation filter as its digital signal processor (DSP). The DS-ADC is characterized and implemented using Tanner tools and LTSpice tool. |
| format |
text |
| author |
Abad, Alexander C. Yap, Roderick Y. |
| author_facet |
Abad, Alexander C. Yap, Roderick Y. |
| author_sort |
Abad, Alexander C. |
| title |
Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter |
| title_short |
Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter |
| title_full |
Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter |
| title_fullStr |
Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter |
| title_full_unstemmed |
Design of a low voltage bipolar delta-sigma ADC with CIC decimation filter |
| title_sort |
design of a low voltage bipolar delta-sigma adc with cic decimation filter |
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Animo Repository |
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2011 |
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https://animorepository.dlsu.edu.ph/faculty_research/12094 |
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1800918920503230464 |