Enhanced implementation of a pipelined FFT processor in NI-labVIEW FPGA

• Main Authors: Bernardo, Neil Irwin M., Umali, Edwin M., Lorenzo, Romarie U., Paet, Leonard B., Marciano, Joel Joseph S., Jr.
• Format: text
• Published: Animo Repository 2014
• Subjects: Field programmable gate arrays; Fourier transformations; Electrical and Computer Engineering
• Online Access: https://animorepository.dlsu.edu.ph/faculty_research/12567
• Institution: De La Salle University

This paper presents an enhanced implementation of a FFT processor in NI-LabVIEW FPGA. The proposed FFT processor implementation uses Radix-22 Single path Delay Feedback FFT architecture to allow fast and continuous flow of input data while performing DFT operation. As optimal bit-reversal circuit was used to shuffle the FFT output to its correct sequence. The FFT processor was tested ona PXIe-7965R FPGA. FPGA resource utilization and latency were measured for different number of FFT points. FPGA resource utilization and latency data were compared to that of LabVIEW FFT Express VI. It is shown from the results that the proposed FFT processor implementation has minimal FPGA slice utilization (around 16.4% of total FPGA slides available in PXIe-7865R) in exchange for additional Block RAM usage. Incorporating pipelining reduced the measured latency values of the proposed implementation to below 50& of the latency values of the LabVIEW FFT Express VI. Overall, the proposed FFT processor implementation has significant improvement over the LabVIEW FFT Express VI in terms of FPGA slide usage and latency.