Enhanced implementation of a pipelined FFT processor in NI-labVIEW FPGA

• Main Authors: Bernardo, Neil Irwin M., Umali, Edwin M., Lorenzo, Romarie U., Paet, Leonard B., Marciano, Joel Joseph S., Jr.
• Format: text
• Published: Animo Repository 2014
• Subjects: Field programmable gate arrays; Fourier transformations; Electrical and Computer Engineering
• Online Access: https://animorepository.dlsu.edu.ph/faculty_research/12567
• Institution: De La Salle University

This paper presents an enhanced implementation of a FFT processor in NI-LabVIEW FPGA. The proposed FFT processor implementation uses Radix-22 Single path Delay Feedback FFT architecture to allow fast and continuous flow of input data while performing DFT operation. As optimal bit-reversal circuit wa...