Reliable 3-D clock-tree synthesis considering nonlinear capacitive TSV model with electrical–thermal–mechanical coupling

• Main Authors: P. D., Sai Manoj, Yu, Hao, Yang Shang, Chuan Seng Tan, Sung Kyu Lim
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Computer science and engineering::Computer applications::Computer-aided engineering
• 在線閱讀: https://hdl.handle.net/10356/100898; http://hdl.handle.net/10220/18217

A robust physical design of 3-D IC requires investigation on through-silicon via (TSV). The large temperatures and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as a resistor with linear electrical-thermal dependence, which ignores the...