Design and characterization of low loss 50 picoseconds delay line on SOI platform

Design and characterization of low loss 50 picoseconds delay line on SOI platform

We design and experimentally demonstrate 50 picoseconds (ps) low loss delay line on 300 nm SOI platform. The delay line unit consists of straight rib waveguide and strip bend section linked by a transition taper waveguide. Low propagation loss of ~0.1 dB/cm is achieved on the straight rib waveguide....

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Bibliographic Details
Main Authors: Xiao, Zhe, Luo, Xianshu, Liow, Tsung-Yang, Lim, Peng Huei, Prabhathan, Patinharekandy, Zhang, Jing, Luan, Feng
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2013
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Optics, optoelectronics, photonics
Online Access:https://hdl.handle.net/10356/101191
http://hdl.handle.net/10220/18290
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Institution: Nanyang Technological University
Language: English
Description
Summary:We design and experimentally demonstrate 50 picoseconds (ps) low loss delay line on 300 nm SOI platform. The delay line unit consists of straight rib waveguide and strip bend section linked by a transition taper waveguide. Low propagation loss of ~0.1 dB/cm is achieved on the straight rib waveguide. With taking into account both low loss and desirable delay, a complete design and characterization process for passive delay line is presented. Our measurement results show that about 0.7 dB excess loss is achievable for 50 ps delay. The loss can be further reduced by adjusting the layout parameters.

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