Modulation of capacitance magnitude by charging/discharging in silicon nanocrystals distributed throughout the gate oxide in MOS structures

• Main Authors: Gui, D., Ng, Chi Yung, Chen, Tupei, Liu, Yang, Tse, Man Siu
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics
• Online Access: https://hdl.handle.net/10356/101350; http://hdl.handle.net/10220/6428
• Institution: Nanyang Technological University

In this work, charge trapping in silicon nanocrystals (nc-Si) distributed throughout the gate oxide in a metal oxide semiconductor (MOS) structure has been studied. This situation is different from the conventional one with nc-Si confined in a narrow layer embedded in the gate oxide. In the latter, charge trapping in nc-Si leads to a shift in capacitance-voltage characteristic (i.e., a change in the flat-band voltage). In contrast, in the former the charge trapping leads to a dramatic reduction in the MOS capacitance. The original capacitance could be recovered after the release of the trapped charges by a small bias, UV light illumination, or low-temperature thermal annealing.