A low-power single-phase clock multiband flexible divider
In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology. The multiband divider consists of a proposed...
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sg-ntu-dr.10356-1016692020-03-07T14:00:34Z A low-power single-phase clock multiband flexible divider Manthena, Vamshi Krishna Do, Manh Anh Boon, Chirn Chye Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply. 2013-10-17T02:33:39Z 2019-12-06T20:42:34Z 2013-10-17T02:33:39Z 2019-12-06T20:42:34Z 2012 2012 Journal Article Manthena, V. K., Do, M. A., Boon, C. C., & Yeo, K. S. (2012). A low-power single-phase clock multiband flexible divider. IEEE transactions on very large scale integration (VLSI) systems, 20(2), 376-380. 1063-8210 https://hdl.handle.net/10356/101669 http://hdl.handle.net/10220/16540 10.1109/TVLSI.2010.2100052 en IEEE transactions on very large scale integration (VLSI) systems © 2011 IEEE |
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DRNTU::Engineering::Electrical and electronic engineering Manthena, Vamshi Krishna Do, Manh Anh Boon, Chirn Chye Yeo, Kiat Seng A low-power single-phase clock multiband flexible divider |
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In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Manthena, Vamshi Krishna Do, Manh Anh Boon, Chirn Chye Yeo, Kiat Seng |
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Article |
author |
Manthena, Vamshi Krishna Do, Manh Anh Boon, Chirn Chye Yeo, Kiat Seng |
author_sort |
Manthena, Vamshi Krishna |
title |
A low-power single-phase clock multiband flexible divider |
title_short |
A low-power single-phase clock multiband flexible divider |
title_full |
A low-power single-phase clock multiband flexible divider |
title_fullStr |
A low-power single-phase clock multiband flexible divider |
title_full_unstemmed |
A low-power single-phase clock multiband flexible divider |
title_sort |
low-power single-phase clock multiband flexible divider |
publishDate |
2013 |
url |
https://hdl.handle.net/10356/101669 http://hdl.handle.net/10220/16540 |
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1681047217248403456 |