Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler

• Main Authors: Yeo, Kiat Seng, Boon, Chirn Chye, Lim, Wei Meng, Do, Manh Anh, Krishna, Manthena Vamshi
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: https://hdl.handle.net/10356/91237; http://hdl.handle.net/10220/6213
• 機構: Nanyang Technological University

In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which i...