Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler

• Main Authors: Yeo, Kiat Seng, Boon, Chirn Chye, Lim, Wei Meng, Do, Manh Anh, Krishna, Manthena Vamshi
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/91237; http://hdl.handle.net/10220/6213
• Institution: Nanyang Technological University

In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a Chartered 0.18 m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.