IP-enabled C/C++ based high level synthesis : a step towards better designer productivity and design performance
Intellectual property (IP) core based design is an emerging design methodology to deal with increasing chip design complexity. C/C++ based high level synthesis (HLS) is also gaining traction as a design methodology to deal with increasing design complexity. In the work presented here, we present a d...
Saved in:
Main Authors: | Sinha, Sharad, Srikanthan, Thambipillai |
---|---|
Other Authors: | School of Computer Engineering |
Format: | Article |
Language: | English |
Published: |
2014
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/102194 http://hdl.handle.net/10220/18835 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis
by: Sinha, Sharad, et al.
Published: (2014) -
Dataflow graph partitioning for high level synthesis
by: Sinha, Sharad, et al.
Published: (2013) -
Rapid memory-aware selection of hardware accelerators in programmable SoC design
by: Prakash, Alok, et al.
Published: (2019) -
Intelligent high level synthesis for customization on reconfigurable platforms
by: Sharad Sinha
Published: (2014) -
Enabling green product design with TRIZ
by: Tai, Marcus Jia En
Published: (2012)