Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis

• المؤلفون الرئيسيون: Sinha, Sharad, Srikanthan, Thambipillai
• مؤلفون آخرون: School of Computer Engineering
• التنسيق: مقال
• اللغة: English
• منشور في: 2014
• الموضوعات: DRNTU::Engineering::Computer science and engineering::Theory of computation
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/103095; http://hdl.handle.net/10220/24439
• المؤسسة: Nanyang Technological University

Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This...