Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis

• Main Authors: Sinha, Sharad, Srikanthan, Thambipillai
• Other Authors: School of Computer Engineering
• Format: Article
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Computer science and engineering::Theory of computation
• Online Access: https://hdl.handle.net/10356/103095; http://hdl.handle.net/10220/24439
• Institution: Nanyang Technological University

Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This paper proposes algorithms for automatically identifying the different types of multiplication operations and investigates the ensemble of these different types of multiplication operations. This distinguishes it from previous works where mapping strategies for an individual type of multiplication operation have been investigated and the type of multiplication operation is assumed to be known a priori. A new cost model, independent of device and synthesis tools, for establishing priority among different types of multiplication operations for mapping to on-chip DSP blocks is also proposed. This cost model is used by a proposed analysis and priority ordering based mapping strategy targeted at making efficient use of hard DSP blocks on FPGAs while maximizing the operating frequency of designs. Results show that the proposed methodology could result in designs which were at least 2× faster in performance than those generated by commercial HLS tool: Vivado-HLS.