Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis

• Main Authors: Sinha, Sharad, Srikanthan, Thambipillai
• Other Authors: School of Computer Engineering
• Format: Article
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Computer science and engineering::Theory of computation
• Online Access: https://hdl.handle.net/10356/103095; http://hdl.handle.net/10220/24439
• Institution: Nanyang Technological University

Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This...