Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis

Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This...

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Main Authors: Sinha, Sharad, Srikanthan, Thambipillai
Other Authors: School of Computer Engineering
Format: Article
Language:English
Published: 2014
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Online Access:https://hdl.handle.net/10356/103095
http://hdl.handle.net/10220/24439
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1030952020-05-28T07:17:17Z Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis Sinha, Sharad Srikanthan, Thambipillai School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Theory of computation Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This paper proposes algorithms for automatically identifying the different types of multiplication operations and investigates the ensemble of these different types of multiplication operations. This distinguishes it from previous works where mapping strategies for an individual type of multiplication operation have been investigated and the type of multiplication operation is assumed to be known a priori. A new cost model, independent of device and synthesis tools, for establishing priority among different types of multiplication operations for mapping to on-chip DSP blocks is also proposed. This cost model is used by a proposed analysis and priority ordering based mapping strategy targeted at making efficient use of hard DSP blocks on FPGAs while maximizing the operating frequency of designs. Results show that the proposed methodology could result in designs which were at least 2× faster in performance than those generated by commercial HLS tool: Vivado-HLS. Published version 2014-12-11T07:27:35Z 2019-12-06T21:05:29Z 2014-12-11T07:27:35Z 2019-12-06T21:05:29Z 2014 2014 Journal Article Sinha, S., & Srikanthan, T. (2014). Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis. International journal of reconfigurable computing, 2014, 1-14. https://hdl.handle.net/10356/103095 http://hdl.handle.net/10220/24439 10.1155/2014/564924 en International journal of reconfigurable computing © 2014 Sharad Sinha and Thambipillai Srikanthan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 15 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Computer science and engineering::Theory of computation
spellingShingle DRNTU::Engineering::Computer science and engineering::Theory of computation
Sinha, Sharad
Srikanthan, Thambipillai
Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis
description Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This paper proposes algorithms for automatically identifying the different types of multiplication operations and investigates the ensemble of these different types of multiplication operations. This distinguishes it from previous works where mapping strategies for an individual type of multiplication operation have been investigated and the type of multiplication operation is assumed to be known a priori. A new cost model, independent of device and synthesis tools, for establishing priority among different types of multiplication operations for mapping to on-chip DSP blocks is also proposed. This cost model is used by a proposed analysis and priority ordering based mapping strategy targeted at making efficient use of hard DSP blocks on FPGAs while maximizing the operating frequency of designs. Results show that the proposed methodology could result in designs which were at least 2× faster in performance than those generated by commercial HLS tool: Vivado-HLS.
author2 School of Computer Engineering
author_facet School of Computer Engineering
Sinha, Sharad
Srikanthan, Thambipillai
format Article
author Sinha, Sharad
Srikanthan, Thambipillai
author_sort Sinha, Sharad
title Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis
title_short Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis
title_full Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis
title_fullStr Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis
title_full_unstemmed Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis
title_sort architecture and application-aware management of complexity of mapping multiplication to fpga dsp blocks in high level synthesis
publishDate 2014
url https://hdl.handle.net/10356/103095
http://hdl.handle.net/10220/24439
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