Architecture and application-aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis

Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This...

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Bibliographic Details
Main Authors: Sinha, Sharad, Srikanthan, Thambipillai
Other Authors: School of Computer Engineering
Format: Article
Language:English
Published: 2014
Subjects:
Online Access:https://hdl.handle.net/10356/103095
http://hdl.handle.net/10220/24439
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Institution: Nanyang Technological University
Language: English

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