High performance architecture for move generation in computer chess : an FPGA based implementation

• 主要作者: De Silva, C. R.
• 其他作者: Amarasinghe, S. K.
• 格式: Theses and Dissertations
• 出版: 2008
• 主題: DRNTU::Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence; DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
• 在線閱讀: http://hdl.handle.net/10356/4214
• 機構: Nanyang Technological University

This thesis describes the design of a high performance parallel move generator architecture suitable for a high-speed chess computer. It illustrates how the complicated single task of chess move generation can be decomposed into several simple and independent atomic processors. These processors are...