High performance architecture for move generation in computer chess : an FPGA based implementation

This thesis describes the design of a high performance parallel move generator architecture suitable for a high-speed chess computer. It illustrates how the complicated single task of chess move generation can be decomposed into several simple and independent atomic processors. These processors are...

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Bibliographic Details
Main Author:	De Silva, C. R.
Other Authors:	Amarasinghe, S. K.
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Online Access:	http://hdl.handle.net/10356/4214
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-4214
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spelling	sg-ntu-dr.10356-42142023-07-04T15:12:08Z High performance architecture for move generation in computer chess : an FPGA based implementation De Silva, C. R. Amarasinghe, S. K. School of Electrical and Electronic Engineering DRNTU::Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems This thesis describes the design of a high performance parallel move generator architecture suitable for a high-speed chess computer. It illustrates how the complicated single task of chess move generation can be decomposed into several simple and independent atomic processors. These processors are then implemented in hardware, enabling them to operate in parallel contributing to the overall system throughput. Two novel concepts that contribute mostly to high performance architecture are introduced in this thesis. Master of Engineering 2008-09-17T09:46:52Z 2008-09-17T09:46:52Z 1999 1999 Thesis http://hdl.handle.net/10356/4214 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
spellingShingle	DRNTU::Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems De Silva, C. R. High performance architecture for move generation in computer chess : an FPGA based implementation
description	This thesis describes the design of a high performance parallel move generator architecture suitable for a high-speed chess computer. It illustrates how the complicated single task of chess move generation can be decomposed into several simple and independent atomic processors. These processors are then implemented in hardware, enabling them to operate in parallel contributing to the overall system throughput. Two novel concepts that contribute mostly to high performance architecture are introduced in this thesis.
author2	Amarasinghe, S. K.
author_facet	Amarasinghe, S. K. De Silva, C. R.
format	Theses and Dissertations
author	De Silva, C. R.
author_sort	De Silva, C. R.
title	High performance architecture for move generation in computer chess : an FPGA based implementation
title_short	High performance architecture for move generation in computer chess : an FPGA based implementation
title_full	High performance architecture for move generation in computer chess : an FPGA based implementation
title_fullStr	High performance architecture for move generation in computer chess : an FPGA based implementation
title_full_unstemmed	High performance architecture for move generation in computer chess : an FPGA based implementation
title_sort	high performance architecture for move generation in computer chess : an fpga based implementation
publishDate	2008
url	http://hdl.handle.net/10356/4214
_version_	1772826400791724032

High performance architecture for move generation in computer chess : an FPGA based implementation

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