A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels
The scrutiny of the class of Reed-Solomon (RS) based quasi-cyclic (QC) low-density parity-check (LDPC) codes has inspired the authors to propose a memory efficient mirror-paradigm (MP) RS-based QC-LDPC code by exploiting the geometrical properties from the RS-based QC-LDPC nomenclature. Without any...
Saved in:
| Main Authors: | , , |
|---|---|
| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2013
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/103596 http://hdl.handle.net/10220/16899 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | The scrutiny of the class of Reed-Solomon (RS) based quasi-cyclic (QC) low-density parity-check (LDPC) codes has inspired the authors to propose a memory efficient mirror-paradigm (MP) RS-based QC-LDPC code by exploiting the geometrical properties from the RS-based QC-LDPC nomenclature. Without any loss in performance, the proposed MPRS-based QC-LDPC code delivers discernible memory savings that address the concerns of hefty H-matrices associated to lengthy codewords for non-volatile memory (NVM) applications. Besides, the MPRS-based QC-LDPC codes are not confined to any particular hardware implementation and are compatible with various decoder architectures to complement other optimization schemes. |
|---|