A comparative study on asynchronous Quasi-Delay-Insensitive templates

• Main Authors: Chang, Kok-Leong, Lin, Tong, Ho, Weng-Geng, Chong, Kwen-Siong, Gwee, Bah Hwee, Chang, Joseph Sylvester
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Online Access: https://hdl.handle.net/10356/106111; http://hdl.handle.net/10220/17938; http://dx.doi.org/10.1109/ISCAS.2012.6271621
• Institution: Nanyang Technological University

The robustness of asynchronous logic has proved useful in dealing with contemporary problems in CMOS design such as process variations and power management. However, the general cryptic nature of asynchronous logic has stymied the widespread acceptance of this alternate design technique. Fortunately, the semi-custom approach to asynchronous design reduces the tedious handcrafting efforts that are often non-trivial in large system-on-chips (SoCs). However, even with the adoption of this design approach requires careful selection of asynchronous templates that will suit overall system needs. Therefore in this paper, the most eminent Quasi-Delay-Insensitive asynchronous template families reported to date will be presented, and followed by an in-depth comparison of various design FOMs - template area, static/dynamic capacity, cycle time, latency, throughput and Et2. The most aggressive template (EESTFB) can reach a maximum throughput of 3.56Giga items/s on 0.13µm @ 1.2V.