Ultra low power asynchronous-logic quasi-delay-insensitive circuit design

• Main Author: Ho, Weng Geng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Theses and Dissertations
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/68838
• Institution: Nanyang Technological University

This thesis pertains to the investigation of low power, high robustness and yet speed-efficient digital electronics for portable/mobile/secured applications. We adopt the esoteric asynchronous-logic (async) vis-à-vis the conventional synchronous-logic (sync); more specifically, the async quasi-delay...