Ultra low power asynchronous-logic quasi-delay-insensitive circuit design

• Main Author: Ho, Weng Geng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Theses and Dissertations
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/68838
• Institution: Nanyang Technological University

This thesis pertains to the investigation of low power, high robustness and yet speed-efficient digital electronics for portable/mobile/secured applications. We adopt the esoteric asynchronous-logic (async) vis-à-vis the conventional synchronous-logic (sync); more specifically, the async quasi-delay-insensitive (QDI) gate-level pipeline micro cell templates. In this thesis, there are three proposed QDI cell templates, namely low power improved Sense-Amplifier-based Pass Transistor Logic (iSAPTL), sub-threshold Autonomous Signal-Validity HalfBuffer (ASVHB) and high-speed Sense-Amplifier Half-Buffer (SAHB), which can be applied to portable/mobile/secured applications. An async network-on-chip (ANoC) based on SAHB cell template is further proposed for multi-core systemon-chip (SoC) platform, which is targeted for highly secured cryptography applications. First, we present an async 16×16-bit pipeline multiplier based on our proposed iSAPTL with emphases on low power and high energy-delay efficiencies. The multiplier is designed as part of an async multi-core SoC. Based on the simulations @1V, 65nm CMOS process, the async iSAPTL 16×16-bit pipeline multiplier features, on average, 31% faster speed and 21% lower energy per operation, achieving an overall of 46% lower energy-delay product. It also features 16% lesser number of transistors when compared to reported SAPTL approaches. Second, we propose an async QDI ASVHB realization approach for subthreshold operation (VDD = 0.2V). We compare our ASVHB realization approach against the competitive reported Weak-Conditioned Half-Buffer (WCHB) and Pre-Charged Half-Buffer (PCHB) realization approaches. The ASVHB library cells, on average, features ~52% and ~47% lesser transistors than the WCHB and PCHB library cells. With respect to a 3-stage pipeline realization, the ASVHB pipeline, on average, features ~44% and ~33% lesser switching transitions per cycle than the WCHB and PCHB pipelines respectively. We further design an async 32-bit ALU based on the proposed ASVHB realization approach (@65nm CMOS process). Our ASVHB ALU occupies 0.092mm2 and outperforms the WCHB and PCHB counterparts in terms of transistor-count, energy dissipation and data throughput. Overall, our proposed ASVHB design features ~41% and ~29% lesser transistors respectively than the WCHB and PCHB counterparts. At the sub-threshold operating voltage of VDD = 0.2V, our design dissipates ~41% and ~62% lower energy respectively, and features ~5% and ~37% faster throughput than the WCHB and PCHB counterparts respectively. Third, we propose a novel async QDI SAHB cell design approach, with emphasis on high processing speed (~GHz), high operational robustness and yet low energy dissipation. When six rudimentary library cells embodying our proposed SAHB are compared against the conventional async QDI PCHB approach, at nominal voltage of VDD = 1V @1GHz, SAHB collectively features simultaneously ~64% lower power, ~21% faster and ~6% smaller IC-area. Three 64-bit Kogge-Stone (KS) pipeline adders based on SAHB, PCHB and sync approaches (@65nm CMOS) are designed. Both async QDI designs feature same excellent operational robustness. For 1GHz throughput and at nominal VDD of 1.2V, the design based on the SAHB approach features simultaneously ~56% lower energy and ~24% lower transistor-count against PCHB approach. When benchmarked against the ubiquitous sync counterpart which requires worse case timing assumptions, our SAHB dissipates ~39% lower energy at 1GHz throughput but at the expense of ~2× more transistor-count. Fourth, we propose an 18-bit ANoC router with 5 dual-ports based on the proposed QDI SAHB realization approach for highly secured cryptography applications. We realize the proposed ANoC router (@65nm CMOS), and benchmark it against the reported ANoC router embodying the reported WCHB QDI realization approach. Both our proposed and reported designs feature the high operational robustness. However, our design dissipates 41% lesser energy and occupies 21% smaller area than the reported WCHB counterpart. Overall, the proposed ANoC router occupies 0.105 mm2 and can operate at sub-threshold voltage of 0.3V. At VDD=0.3V, it dissipates 44 fJ per bit and operates at 105 ns per flit.