A fast and compact circuit for integer square root computation based on Mitchell logarithmic method

• Main Authors: Low, Joshua Yung Lih, Jong, Ching Chuen, Low, Jeremy Yung Shern, Tay, Thian Fatt, Chang, Chip Hong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/106483; http://hdl.handle.net/10220/17744; http://dx.doi.org/10.1109/ISCAS.2012.6271459
• Institution: Nanyang Technological University

A novel non-iterative circuit for computing integer square root based on logarithm is proposed in the paper. Mitchell's methods are used for the logarithmic and antilogarithmic conversions. The proposed method merges two conversion stages into a single one to achieve better accuracy with a compact architecture. Hence, the circuit size and latency are reduced. Compared to an existing design based on the modified Dijkstra algorithm used in a coherent receiver, the proposed design is either 8 times smaller or 9 times faster for 16-bit integer input.