Energy-efficient spread second capacitor capacitive DAC for SAR ADC

• Main Authors: Kim, Ju Eon, Lee, Sung-Min, Yoo, Taegeun, Jo, Yong-Jun, Baek, Kwang-Hyun
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: Energy Efficient DAC; Engineering::Electrical and electronic engineering; Low Power
• Online Access: https://hdl.handle.net/10356/106771; http://hdl.handle.net/10220/48974; http://dx.doi.org/10.5573/JSTS.2017.17.6.786
• Institution: Nanyang Technological University

An energy-efficient capacitive digital-to-analog converter (C-DAC) switching with spread second capacitor is proposed for low power successive approximation register analog-to-digital converters (SAR ADCs). In the proposed spread second capacitor capacitive digital-to-analog converter (SSC C-DAC), all capacitors except the most significant bit (MSB) capacitor are switched after the second bit decision. Because the burden of the second capacitor switching is shared with all capacitors except the MSB capacitor, the number of unit capacitors and the burden of driving VCM are reduced. The proposed SSC C-DAC achieves 98.1% more efficient switching energy and can be comprised of the number of quarter unit capacitors, contrary to that in conventional schemes. The fabricated differential-type SAR ADC with SSC C-DAC has a 10-bit resolution and 10-MS/s sampling speed in 0.18-μm CMOS process. The test results show a SFDR of 60.9 dBc, a SINAD of 53.1 dB and an ENOB of 8.5 bit.