Design of a rail-to-rail input-output analog buffer with high PSRR

This project presents the design of an analog buffer in 0.18µm CMOS technology. The buffer has the capability to source and sink 100mA load current, and to handle rail to rail input and output voltage swings. The design is implemented with the architecture of a folded cascode operational amplifie...

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Bibliographic Details
Main Author: Liu, Ziming
Other Authors: Siek Liter
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2020
Subjects:
Online Access:https://hdl.handle.net/10356/140275
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Institution: Nanyang Technological University
Language: English
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