Study of stress in advanced interconnect systems (nano CMOS device and process technology)

Several studies have illustrated that the assumption of robust SM performance of Cu is optimistic because of its strong dependency on process and structure. Stress-induced voiding (SIV) is one of the most important reliability aspects in Cu dual damascene interconnects. SIV has been a rather difficu...

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Main Author: Pey, Kin Leong.
Other Authors: School of Electrical and Electronic Engineering
Format: Research Report
Language:English
Published: 2008
Subjects:
Online Access:http://hdl.handle.net/10356/14179
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-141792023-03-04T03:21:42Z Study of stress in advanced interconnect systems (nano CMOS device and process technology) Pey, Kin Leong. School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics Several studies have illustrated that the assumption of robust SM performance of Cu is optimistic because of its strong dependency on process and structure. Stress-induced voiding (SIV) is one of the most important reliability aspects in Cu dual damascene interconnects. SIV has been a rather difficult reliability problem to address quantitatively since its first observation in 1984. Stress plays a dominant role but must be combined with other factors to understand and quantify stress migration. The purpose for this project is to develop a simulation model based on a three dimensional (3D) finite element analysis (FEA) to study the stress distribution of a gouging via. Wide bottom metal lead Cu damascene interconnects with its interconnecting Cu via gouged 400Å into its underlying metal lead was brought into the picture, and used throughout this study. Firstly, systematic studies were conducted to evaluate the stress- induced voiding mechanism under a Cu via placed over a wide metal lead from stress migration test with no electrical bias. The impact of geometrical features such as via location, metal line width and design aspects of interconnects on the stress distribution migration were studied and tested, by using the ANSYS commercial software. The effect of low-k dielectric materials on the hydrostatic stress which led to stress migration voiding inside a gauging Cu via was also analyzed. The hydrostatic stress contour plots of Cu/FSG and Cu/low-k damascene interconnect with different structure design as mentioned above were shown and the related issues were discussed. Dual-via interconnects were proven to improve SM performance. The effect of gauging via on the SM performance of Cu interconnects was also discussed. 2008-11-06T00:39:39Z 2008-11-06T00:39:39Z 2007 2007 Research Report http://hdl.handle.net/10356/14179 en 83 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics
Pey, Kin Leong.
Study of stress in advanced interconnect systems (nano CMOS device and process technology)
description Several studies have illustrated that the assumption of robust SM performance of Cu is optimistic because of its strong dependency on process and structure. Stress-induced voiding (SIV) is one of the most important reliability aspects in Cu dual damascene interconnects. SIV has been a rather difficult reliability problem to address quantitatively since its first observation in 1984. Stress plays a dominant role but must be combined with other factors to understand and quantify stress migration. The purpose for this project is to develop a simulation model based on a three dimensional (3D) finite element analysis (FEA) to study the stress distribution of a gouging via. Wide bottom metal lead Cu damascene interconnects with its interconnecting Cu via gouged 400Å into its underlying metal lead was brought into the picture, and used throughout this study. Firstly, systematic studies were conducted to evaluate the stress- induced voiding mechanism under a Cu via placed over a wide metal lead from stress migration test with no electrical bias. The impact of geometrical features such as via location, metal line width and design aspects of interconnects on the stress distribution migration were studied and tested, by using the ANSYS commercial software. The effect of low-k dielectric materials on the hydrostatic stress which led to stress migration voiding inside a gauging Cu via was also analyzed. The hydrostatic stress contour plots of Cu/FSG and Cu/low-k damascene interconnect with different structure design as mentioned above were shown and the related issues were discussed. Dual-via interconnects were proven to improve SM performance. The effect of gauging via on the SM performance of Cu interconnects was also discussed.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Pey, Kin Leong.
format Research Report
author Pey, Kin Leong.
author_sort Pey, Kin Leong.
title Study of stress in advanced interconnect systems (nano CMOS device and process technology)
title_short Study of stress in advanced interconnect systems (nano CMOS device and process technology)
title_full Study of stress in advanced interconnect systems (nano CMOS device and process technology)
title_fullStr Study of stress in advanced interconnect systems (nano CMOS device and process technology)
title_full_unstemmed Study of stress in advanced interconnect systems (nano CMOS device and process technology)
title_sort study of stress in advanced interconnect systems (nano cmos device and process technology)
publishDate 2008
url http://hdl.handle.net/10356/14179
_version_ 1759855064067866624