Study of stress in advanced interconnect systems (nano CMOS device and process technology)

• Main Author: Pey, Kin Leong.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Research Report
• Language: English
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics
• Online Access: http://hdl.handle.net/10356/14179
• Institution: Nanyang Technological University

Several studies have illustrated that the assumption of robust SM performance of Cu is optimistic because of its strong dependency on process and structure. Stress-induced voiding (SIV) is one of the most important reliability aspects in Cu dual damascene interconnects. SIV has been a rather difficu...