Study of stress in advanced interconnect systems (nano CMOS device and process technology)

• 主要作者: Pey, Kin Leong.
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Research Report
• 語言: English
• 出版: 2008
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics
• 在線閱讀: http://hdl.handle.net/10356/14179
• 機構: Nanyang Technological University

Several studies have illustrated that the assumption of robust SM performance of Cu is optimistic because of its strong dependency on process and structure. Stress-induced voiding (SIV) is one of the most important reliability aspects in Cu dual damascene interconnects. SIV has been a rather difficu...