A calibration-free/DEM-free 8-bit 2.4-GS/s single-core digital-to-analog converter with a distributed biasing scheme

• Main Authors: Juanda, Shu, Wei, Chang, Joseph Sylvester
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering; Current Steering; Data Conversion
• Online Access: https://hdl.handle.net/10356/142507
• Institution: Nanyang Technological University

This paper describes a calibration-free/dynamic-element-matching-free 8-bit 2.4-GS/s single-core current-steering digital-to-analog converter (CS-DAC) featuring an integral nonlinearity of ±0.097 LSB (equivalent to 11-bit accuracy), a differential nonlinearity of 0.15/-0.05 LSB, a spurious-free dynamic range of >47.8 dB across the Nyquist bandwidth of 1.13 GHz, and a power dissipation of 26.4 mW from 1.2-/2-V supplies. These attributes are achieved by our proposed distributed biasing scheme, which largely decouples two critical tradeoffs in the CS-DAC - the tradeoff between the output impedance of the current sources and their current mismatches and that between the current mismatches and the timing errors. To simplify the CS-DAC measurements and hence reduced costs associated with testing during manufacturing, we propose a custom built-in × 2.4-Gb/s digital pattern generator (DPG) featuring low I/O pin count, no high-speed data I/O circuits, and low hardware complexity/size. The proposed 8-bit 2.4-GS/s CS-DAC with the built-in DPG is realized using a commercial 65-nm low-power CMOS process.