An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS

• Main Authors: Do, Anh Tuan, Seyed Mohammad Ali Zeinolabedin, Jeon, Dongsuk, Sylvester, Dennis, Kim, Tony Tae-Hyoung
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering; Low Power; Neural Recording
• Online Access: https://hdl.handle.net/10356/142509
• Institution: Nanyang Technological University

This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller are...