An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS

An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS

This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller are...

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Main Authors: Do, Anh Tuan, Seyed Mohammad Ali Zeinolabedin, Jeon, Dongsuk, Sylvester, Dennis, Kim, Tony Tae-Hyoung
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2020
Subjects:
Engineering::Electrical and electronic engineering
Low Power
Neural Recording
Online Access:https://hdl.handle.net/10356/142509
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1425092020-06-23T04:10:18Z An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS Do, Anh Tuan Seyed Mohammad Ali Zeinolabedin Jeon, Dongsuk Sylvester, Dennis Kim, Tony Tae-Hyoung School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering Low Power Neural Recording This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are utilized in the detector for dynamic power reduction. Finally, an ultralow-voltage 8T static random access memory (SRAM) is developed to reduce area and leakage consumption when compared to D flip-flop -based memory. The proposed SSP, fabricated in 65-nm CMOS process technology, consumes only 0.175 μW/channel when processing 128 input channels at 3.2 MHz and 0.54 V, which is the lowest among the compared state-of-the-art SSPs. The proposed SSP also occupies 0.003 mm2/channel, which allows 333 channels/mm2. 2020-06-23T04:10:18Z 2020-06-23T04:10:18Z 2018 Journal Article Do, A. T., Seyed Mohammad Ali Zeinolabedin, Jeon, D., Sylvester, D., & Kim, T. T.-H. (2019). An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(1), 126-137. doi:10.1109/TVLSI.2018.2875934 1063-8210 https://hdl.handle.net/10356/142509 10.1109/TVLSI.2018.2875934 2-s2.0-85056155895 1 27 126 137 en IEEE Transactions on Very Large Scale Integration (VLSI) Systems © 2018 IEEE. All rights reserved.
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
Low Power
Neural Recording
spellingShingle Engineering::Electrical and electronic engineering
Low Power
Neural Recording
Do, Anh Tuan
Seyed Mohammad Ali Zeinolabedin
Jeon, Dongsuk
Sylvester, Dennis
Kim, Tony Tae-Hyoung
An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS
description This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are utilized in the detector for dynamic power reduction. Finally, an ultralow-voltage 8T static random access memory (SRAM) is developed to reduce area and leakage consumption when compared to D flip-flop -based memory. The proposed SSP, fabricated in 65-nm CMOS process technology, consumes only 0.175 μW/channel when processing 128 input channels at 3.2 MHz and 0.54 V, which is the lowest among the compared state-of-the-art SSPs. The proposed SSP also occupies 0.003 mm2/channel, which allows 333 channels/mm2.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Do, Anh Tuan
Seyed Mohammad Ali Zeinolabedin
Jeon, Dongsuk
Sylvester, Dennis
Kim, Tony Tae-Hyoung
format Article
author Do, Anh Tuan
Seyed Mohammad Ali Zeinolabedin
Jeon, Dongsuk
Sylvester, Dennis
Kim, Tony Tae-Hyoung
author_sort Do, Anh Tuan
title An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS
title_short An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS
title_full An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS
title_fullStr An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS
title_full_unstemmed An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS
title_sort area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ w/channel in 65-nm cmos
publishDate 2020
url https://hdl.handle.net/10356/142509
_version_ 1681056752494182400

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