A 311.6 GHz phase-locked loop in 0.13 μm SiGe BiCMOS process with –90 dBc/Hz in-band phase noise

• Main Authors: Liang, Yuan, Boon, Chirn Chye, Chen, Qian, Liu, Zhe, Li, Chenyang, Mausolf, Thomas, Kissinger, Dietmar, Wang, Yong, Ng, Herman Jalli
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits; Terahertz; Quadrature XOR Phase Detector
• Online Access: https://ims-ieee.org/; https://hdl.handle.net/10356/143713
• Institution: Nanyang Technological University

Using a quadrature XOR-gate (QXOR) reduces the second order harmonic term at the output, making it suitable to be used as a phase/frequency detector in high-frequency phase-locked loops. This paper introduces a 320 GHz PLL employing QXOR to cancel the reference spur, suppress in-band noise, and also reduces the power consumption of the frequency tracking loop (FTL). The beat frequency of FTL enables the lock detector (LD) to search the right band for VCO operation. The proposed PLL was implemented in IHP 0.13 μm SiGe BiCMOS process. Measured results show that the PLL achieves a locking range from 307.45 GHz to 321.28 GHz, while consuming 372 mW DC power, with −113.7 dBc/Hz phase noise at 1 MHz offset measured at 40.96 GHz. This leads to an integrated RMS jitter (1k−30MHz) of 72 fs. The measured phase noise at 311.6 GHz is –90 dBc/Hz at 1 MHz offset, with a total division ratio of 512. The measured maximum probed output power is –3.3 dBm. The PLL occupies a 1.4 mm2 area.