A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector
This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer-N phaselocked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs...
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Main Authors: | , , |
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Other Authors: | |
Format: | Article |
Language: | English |
Published: |
2022
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/156847 |
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Institution: | Nanyang Technological University |
Language: | English |