Factorized carry lookahead adders

New factorized carry lookahead adders corresponding to the regular carry lookahead adder (RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the block carry lookahead adder (BCLA) architecture viz. the factorized block carry lookahead adder (FBCLA) are presented. The i...

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Bibliographic Details
Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas Leslie
Other Authors: School of Computer Science and Engineering
Format: Conference or Workshop Item
Language:English
Published: 2020
Subjects:
Online Access:https://hdl.handle.net/10356/144049
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Institution: Nanyang Technological University
Language: English
Description
Summary:New factorized carry lookahead adders corresponding to the regular carry lookahead adder (RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the block carry lookahead adder (BCLA) architecture viz. the factorized block carry lookahead adder (FBCLA) are presented. The idea behind the proposed factorized carry lookahead adders is discussed and example implementations are provided. The RCLA, BCLA, FRCLA and FBCLA were realized using the gates of a 32/28nm CMOS standard digital cell library. The results show that the proposed FRCLA achieves an average reduction in the power-delay product i.e., energy by 7.85% for 32- and 64-bit additions compared to the best among the rest.