Factorized carry lookahead adders
New factorized carry lookahead adders corresponding to the regular carry lookahead adder (RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the block carry lookahead adder (BCLA) architecture viz. the factorized block carry lookahead adder (FBCLA) are presented. The i...
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sg-ntu-dr.10356-1440492020-10-09T08:32:32Z Factorized carry lookahead adders Balasubramanian, Padmanabhan Maskell, Douglas Leslie School of Computer Science and Engineering 14th International Symposium on Signals, Circuits and Systems (ISSCS 2019) Engineering::Computer science and engineering::Hardware Engineering::Electrical and electronic engineering::Integrated circuits Adders Carry Logic New factorized carry lookahead adders corresponding to the regular carry lookahead adder (RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the block carry lookahead adder (BCLA) architecture viz. the factorized block carry lookahead adder (FBCLA) are presented. The idea behind the proposed factorized carry lookahead adders is discussed and example implementations are provided. The RCLA, BCLA, FRCLA and FBCLA were realized using the gates of a 32/28nm CMOS standard digital cell library. The results show that the proposed FRCLA achieves an average reduction in the power-delay product i.e., energy by 7.85% for 32- and 64-bit additions compared to the best among the rest. Ministry of Education (MOE) Accepted version This work is supported by the Ministry of Education (MOE), Singapore under grants MOE2017-T2-1-002 and MOE2018-T2-2-024. 2020-10-09T08:06:19Z 2020-10-09T08:06:19Z 2019 Conference Paper Balasubramanian, P., & Maskell, D. L. (2019). Factorized carry lookahead adders. 14th International Symposium on Signals, Circuits and Systems (ISSCS 2019). doi:10.1109/ISSCS.2019.8801765 978-1-7281-3896-1 https://hdl.handle.net/10356/144049 10.1109/ISSCS.2019.8801765 en MOE2017-T2-1-002 MOE2018-T2-2-024 © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/ISSCS.2019.8801765 application/pdf |
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Engineering::Computer science and engineering::Hardware Engineering::Electrical and electronic engineering::Integrated circuits Adders Carry Logic Balasubramanian, Padmanabhan Maskell, Douglas Leslie Factorized carry lookahead adders |
description |
New factorized carry lookahead adders corresponding to the regular carry lookahead adder (RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the block carry lookahead adder (BCLA) architecture viz. the factorized block carry lookahead adder (FBCLA) are presented. The idea behind the proposed factorized carry lookahead adders is discussed and example implementations are provided. The RCLA, BCLA, FRCLA and FBCLA were realized using the gates of a 32/28nm CMOS standard digital cell library. The results show that the proposed FRCLA achieves an average reduction in the power-delay product i.e., energy by 7.85% for 32- and 64-bit additions compared to the best among the rest. |
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School of Computer Science and Engineering |
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School of Computer Science and Engineering Balasubramanian, Padmanabhan Maskell, Douglas Leslie |
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Conference or Workshop Item |
author |
Balasubramanian, Padmanabhan Maskell, Douglas Leslie |
author_sort |
Balasubramanian, Padmanabhan |
title |
Factorized carry lookahead adders |
title_short |
Factorized carry lookahead adders |
title_full |
Factorized carry lookahead adders |
title_fullStr |
Factorized carry lookahead adders |
title_full_unstemmed |
Factorized carry lookahead adders |
title_sort |
factorized carry lookahead adders |
publishDate |
2020 |
url |
https://hdl.handle.net/10356/144049 |
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1681057522313592832 |