Factorized carry lookahead adders

• Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas Leslie
• 其他作者: School of Computer Science and Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2020
• 主題: Engineering::Computer science and engineering::Hardware; Engineering::Electrical and electronic engineering::Integrated circuits; Adders; Carry Logic
• 在線閱讀: https://hdl.handle.net/10356/144049
• 機構: Nanyang Technological University

New factorized carry lookahead adders corresponding to the regular carry lookahead adder (RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the block carry lookahead adder (BCLA) architecture viz. the factorized block carry lookahead adder (FBCLA) are presented. The idea behind the proposed factorized carry lookahead adders is discussed and example implementations are provided. The RCLA, BCLA, FRCLA and FBCLA were realized using the gates of a 32/28nm CMOS standard digital cell library. The results show that the proposed FRCLA achieves an average reduction in the power-delay product i.e., energy by 7.85% for 32- and 64-bit additions compared to the best among the rest.