A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter

A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter

This paper presents a high speed highly linear energy-efficient constant-slope based voltage-to-time converter (VTC). By combining sample-and-hold with constant charging process, we achieve precise sampled step and linear charging ramp concurrently without using the extra control clock. Simple calib...

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Main Authors: Chen, Qian, Liang, Yuan, Kim, Bongjin, Boon, Chirn Chye
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2020
Subjects:
Engineering::Electrical and electronic engineering::Integrated circuits
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Online Access:https://hdl.handle.net/10356/144407
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1444072020-11-03T07:58:14Z A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter Chen, Qian Liang, Yuan Kim, Bongjin Boon, Chirn Chye School of Electrical and Electronic Engineering 2020 The IEEE International Symposium on Circuits and Systems (ISCAS) Engineering::Electrical and electronic engineering::Integrated circuits Clocks Switches This paper presents a high speed highly linear energy-efficient constant-slope based voltage-to-time converter (VTC). By combining sample-and-hold with constant charging process, we achieve precise sampled step and linear charging ramp concurrently without using the extra control clock. Simple calibration has been implemented to overcome conversion gain variation due to process-voltage-temperature (PVT) variation. The post-layout simulation results show that the SFDR/-THD of the proposed VTC reaches 58.7dB/56.3dB at 3GS/s near Nyquist (typical corner). The VTC achieves 144ps output range with 0.83mW power consumption at 3GHz. It occupies an active area of 41.3um × 34.4um implemented in 65nm CMOS. Ministry of Education (MOE) Accepted version This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 (MOE2019-T2- 1-114). 2020-11-03T07:58:14Z 2020-11-03T07:58:14Z 2020 Conference Paper Chen, Q., Liang, Y., Kim, B., & Boon, C. C. (2020). A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter. Proceedings of the 2020 The IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/ISCAS45731.2020.9180535 https://hdl.handle.net/10356/144407 10.1109/ISCAS45731.2020.9180535 en MOE2019-T2- 1-114 © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work is available at: https://doi.org/10.1109/ISCAS45731.2020.9180535 application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering::Integrated circuits
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spellingShingle Engineering::Electrical and electronic engineering::Integrated circuits
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Chen, Qian
Liang, Yuan
Kim, Bongjin
Boon, Chirn Chye
A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter
description This paper presents a high speed highly linear energy-efficient constant-slope based voltage-to-time converter (VTC). By combining sample-and-hold with constant charging process, we achieve precise sampled step and linear charging ramp concurrently without using the extra control clock. Simple calibration has been implemented to overcome conversion gain variation due to process-voltage-temperature (PVT) variation. The post-layout simulation results show that the SFDR/-THD of the proposed VTC reaches 58.7dB/56.3dB at 3GS/s near Nyquist (typical corner). The VTC achieves 144ps output range with 0.83mW power consumption at 3GHz. It occupies an active area of 41.3um × 34.4um implemented in 65nm CMOS.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Chen, Qian
Liang, Yuan
Kim, Bongjin
Boon, Chirn Chye
format Conference or Workshop Item
author Chen, Qian
Liang, Yuan
Kim, Bongjin
Boon, Chirn Chye
author_sort Chen, Qian
title A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter
title_short A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter
title_full A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter
title_fullStr A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter
title_full_unstemmed A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter
title_sort 3gs/s highly linear energy efficient constant-slope based voltage-to-time converter
publishDate 2020
url https://hdl.handle.net/10356/144407
_version_ 1688665373340073984

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