A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology

• Main Authors: Yi, Xiang, Liang, Zhipeng, Feng, Guangyin, Meng, Fanyi, Wang, Cheng, Li, Chenyang, Yang, Kaituo, Liu, Bei, Boon, Chirn Chye
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering; Cascaded Phase-locked Loop (PLL); Frequency Synthesizer
• Online Access: https://hdl.handle.net/10356/144845
• Institution: Nanyang Technological University

A fully integrated 93.4-104.8-GHz 57-mW fractional-N cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional-N PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm 2 . The measured phase noise of QVCO and PLL is -113.26 and -106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOMT of the QVCO at 10-MHz offset are -178.4 and -180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz.