A study of wireless inter-chip interconnect

• Main Author: Chen, Zhiming
• Other Authors: Zhang Yue Ping
• Format: Theses and Dissertations
• Language: English
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio; DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/14559
• Institution: Nanyang Technological University

In semiconductor industry, device feature dimension has been continuously scaled down to reduce device size and to improve circuit performance. In parallel with the device feature dimension down scaling, the width and thickness of wire interconnect have been reduced. On the other hand, to integrate more functions together, chip size continues growing. Therefore, the down-scaled wire interconnect has to route over an ever increasing chip area, implying degraded interconnect performance. As a matter of fact, performance of interconnects rather than device has become a bottleneck of ICs system performance. With improved radio frequency silicon technologies and higher-degree integration, wireless interconnect, which realizes wireless communications among cores within a chip or different chips within a module, is a viable candidate for solving problems in future generations of interconnects.